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Rev 0; 1/07
High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table
General Description
The DS3501 is a 7-bit, nonvolatile (NV) digital potentiometer featuring an output voltage range of up to 15.5V. Programming is accomplished by an I2C-compatible interface, which can operate at speeds of up to 400kHz. External voltages are applied at the RL and RH inputs to define the lowest and highest potentiometer outputs. The DS3501 contains an on-chip temperature sensor and associated analog-to-digital converter (ADC). The ADC output addresses a 36-word NV lookup table (LUT). The LUT output can drive the pot directly or be added to an NV initial-value register (IVR) to drive the pot. This flexible LUT-based architecture allows the DS3501 to provide a temperature-compensated potentiometer output with arbitrary slope.
Features
o 128 Wiper Tap Points o Full-Scale Resistance: 10k o On-Chip Temperature Sensor and ADC o o o 36-Byte Lookup Table (LUT) I2C-Compatible Serial Interface Address Pins Allow Up to Four DS3501s to Share the Same I2C Bus o Digital Operating Voltage: 2.7V to 5.5V o Analog Operating Voltage: 4.5V to 15.5V o Operating Temperature: -40C to +100C o Pin and Software Compatible with ISL95311 (Default Mode) o 10-Pin SOP Package
DS3501
Applications
TFT-LCD VCOM Calibration Linear and Nonlinear Compensation Instrumentation and Industrial Controls Mechanical POT Replacement Optical Transceivers
Pin Configuration and Typical Operating Circuit appear at end of data sheet.
Ordering Information
PART DS3501U+ DS3501U+T&R TEMP RANGE -40C to +100C -40C to +100C PIN-PACKAGE 10 SOP 10 SOP
+Denotes lead-free package. T&R denotes tape-and-reel.
Functional Diagram
RH 127 SDA SCL VOLATILE WIPER REGISTER 126
125
DS3501
DECODER LEVER SHIFTER 2
NV IVR
36-BYTE LUT NV MEMORY
1
A1 A0
CONTROL CIRCUITRY AND ADDRESS DECODE
0
TEMP SENSOR AND ADC
RL RW
______________________________________________ Maxim Integrated Products
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table DS3501
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Relative to GND ...............-0.5V to +6.0V Voltage Range on V+ Relative to GND ..................-0.5V to +17V Voltage Range on SDA, SCL, A0, A1 Relative to GND..........-0.5V to (VCC + 0.5V), not to exceed 6.0V Voltage Range on RH, RL, RW...................................-0.5V to V+ Voltage Range Across RH and RL Pins .....................-0.5V to V+ Operating Temperature Range .........................-40C to +100C Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature .......................................See IPC/JEDEC J-STD-020 Specification Maximum RW Current ...........................................................1mA
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +100C)
PARAMETER Supply Voltage V+ Voltage Input Logic 1 (SCL, SDA, A0, A1) Input Logic 0 (SCL, SDA, A0, A1) Resistor Inputs (RL, RW, RH) Wiper Current SYMBOL VCC V+ VIH VIL VRES IWIPER (Note 1) V+ > VCC CONDITIONS MIN +2.7 +4.5 0.7 x VCC -0.3 -0.3 TYP MAX +5.5 +15.5 VCC + 0.3 0.3 x VCC V+ + 0.3 1 UNITS V V V V V mA
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +100C, unless otherwise noted.)
PARAMETER VCC Supply Current Standby Supply Current V+ Bias Current Input Leakage (SDA, SCL, A0, A1) Low-Level Output Voltage (SDA) I/O Capacitance Power-Up Recall Voltage Power-Up Memory Recall Delay Wiper Resistance End-to-End Resistance (RH to RL) RTOTAL Tolerance RTOTAL Temp Co. CH, CL, CW Capacitance CPOT SYMBOL ICC ICC2 ISTBY IV+ IL VOL CI/O VPOR tD RW RTOTAL TA = +25C (Note 7) -20 200 10 (Note 5) (Note 6) V+ = 15.0V 10 +20 1.6 3mA sink current -1 0.0 5 (Note 2) (Note 3) (Note 4) CONDITIONS MIN TYP 2 250 40 350 60 +1 +1 0.4 10 2.6 5 5000 MAX UNITS mA A A A A V pF V ms k % ppm pF
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table
TEMPERATURE SENSOR CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +100C, unless otherwise noted.)
PARAMETER Temperature Error Update Rate (Temperature and Supply Conversion Time) tFRAME 16 SYMBOL CONDITIONS MIN TYP MAX 5 UNITS C ms
DS3501
ANALOG VOLTAGE MONITORING CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +100C, unless otherwise noted.)
PARAMETER Supply Resolution Input/Supply Accuracy Input Supply Offset Update Rate (Temperature and Supply Conversion Time) SYMBOL LSB ACC VOS tFRAME CONDITIONS Full-scale voltage of 6.5536V At factory setting (Note 7) MIN TYP 25.6 0.25 0 16 1 5 MAX UNITS mV % FS (Full Scale) LSB ms
VOLTAGE-DIVIDER CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +100C, unless otherwise noted.)
PARAMETER Integral Nonlinearity Differential Nonlinearity Zero-Scale Error Full-Scale Error Ratiometric Temp Coefficient SYMBOL INL DNL ZSERROR FSERROR TCV (Note 8) (Note 9) V+ = 4.5V (Note 10) V+ = 4.5V (Note 11) WR set to 40h CONDITIONS MIN -1 -0.5 0 -2 0.5 -0.003 4 TYP MAX +1 +0.5 2 0 UNITS LSB LSB LSB LSB ppm/C
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +100C, timing referenced to VIL(MAX) and VIH(MIN). See Figure 3.)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL SYMBOL fSCL tBUF tHD:STA tLOW tHIGH (Note 12) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 TYP MAX 400 UNITS kHz s s s s
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table DS3501
I2C AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -40C to +100C, timing referenced to VIL(MAX) and VIH(MIN). See Figure 3.)
PARAMETER Data Hold Time Data Setup Time START Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading EEPROM Write Time Pulse-Width Suppression Time at SDA and SCL Inputs A0, A1 Setup Time A0, A1 Hold Time SDA and SCL Input Buffer Hysteresis SYMBOL tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tW tIN tSU:A tHD:A (Note 13) (Note 14) (Note 15) Before START After STOP 0.6 0.6 0.05 x VCC 10 50 (Note 13) (Note 13) CONDITIONS MIN 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 20 300 300 TYP MAX 0.9 UNITS s ns s ns ns s pF ms ns s s V
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to +5.5V)
PARAMETER EEPROM Write Cycles SYMBOL TA = +70C TA = +25C CONDITIONS MIN 50,000 200,000 TYP MAX UNITS Writes
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative. Note 2: ICC is specified with the following conditions: SCL = 400kHz; SDA pulled up; and RL, RW, RH floating. Note 3: ICC is specified with the following conditions: SCL, SDA pulled up; RL, RW, RH floating; and temperature sensor on. Note 4: ISTBY is specified with SDA = SCL = VCC = 5.5V, resistor pins floating, and CR2 bit 0 = logic-high. Note 5: This is the minimum VCC voltage that causes NV memory to be recalled. Note 6: This is the time from VCC > VPOR until initial memory recall is complete. Note 7: Guaranteed by design. Note 8: Integral nonlinearity is the deviation of a measured resistor setting value from the expected values at each particular resistor setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting. INL = [V(RW)i - (V(RW)0] / LSB(ideal) - i, for i = 0...127. Note 9: Differential nonlinearity is the deviation of the step-size change between two LSB settings from the expected step size. The expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position. DNL = [V(RW)i+1 - (V(RW)i] / LSB(ideal) - 1, for i = 0...126. Note 10: ZS error = code 0 wiper voltage divided by one LSB(ideal). Note 11: FS error = (code 127 wiper voltage - V+) divided by one LSB (ideal). Note 12: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard mode timing. Note 13: CB--total capacitance of one bus line in picofarads. Note 14: EEPROM write time begins after a STOP condition occurs. Note 15: Pulses narrower than max are suppressed. 4 _____________________________________________________________________
High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table DS3501
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS3501 toc01 DS3501 toc02
SUPPLY CURRENT vs. TEMPERATURE
220 SUPPLY CURRENT (A) LUT MODE 170 220 SUPPLY CURRENT (A)
STANDBY SUPPLY CURRENT vs. TEMPERATURE
LUT MODE STANDBY SUPPLY CURRENT (A) 35 DEFAULT MODE 34 33 32 31 30 V+ = 15.5V, VCC = 5V SDA = SCL = VCC; RH, RL, RW ARE FLOATING -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
DS3501 toc03
36
LUT MODE 170
120
DEFAULT MODE
120
DEFAULT MODE
70 V+ = 15.5V, VCC = 5V SDA = SCL = VCC; RH, RL, RW ARE FLOATING -40 -20 0 20 40 60 80 100
70 V+ = 15.5V SDA = SCL = VCC; RL, RH, RW ARE FLOATING 2.7 4.1 SUPPLY VOLTAGE (V) 5.5
20
20
TEMPERATURE (C)
INTEGRAL NONLINEARITY vs. POTENTIOMETER SETTING
DS3501 toc04
DIFFERENTIAL NONLINEARITY vs. POTENTIOMETER SETTING
DS3501 toc05
0.75 0.50 0.25 0 -0.25 -0.50 -0.75 0 16 32 48 64 80 96 112 POTENTIOMETER SETTING (DEC)
0.75 DIFFERENTIAL NONLINEARITY (LSB) 0.50 0.25 0 -0.25 -0.50 -0.75 0 16 32 48 64 80 96 112 POTENTIOMETER SETTING (DEC)
INTEGRAL NONLINEARITY (LSB)
Pin Description
NAME SDA GND VCC A1, A0 RH RW RL V+ SCL PIN 1 2 3 4, 5 6 7 8 9 10 I2C Serial Data. Input/output for I2C data. Ground Terminal Supply Voltage Terminal Address Select Inputs. Determines I2C slave address. Slave address is 01010A1A0X. (See the Slave Address Byte and Address Pins section for details). High Terminal of Potentiometer Wiper Terminal of Potentiometer Low Terminal of Potentiometer Wiper Bias Voltage I2C Serial Clock. Input for I2C clock. DESCRIPTION
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table DS3501
Block Diagrams
V+ VCC GND RH
DS3501
SCL I2C INTERFACE CONTROL LOGIC/ REGISTERS
POS 7Fh
SDA
SEE BIT
A0
WIPER REGISTER/ INITIAL VALUE REGISTER (WR/IVR)
RW
A1
00h POS 00h RL
Default Mode Block Diagram (Update Mode bit = 0)
VCC GND SCL I2C INTERFACE DATA A0 LUT ADDRESS REGISTER TEMP SENSOR ADC VCC VOLTAGE (LUTAR) TEMP 0Ch VCC (V) 0Eh *NOTE THAT WHEN IN LUT OR LUT ADDER MODE, WR IS ACCESSED THROUGH 09h (UNLIKE DEFAULT MODE) WHILE IVR REMAINS AT 00h. 08h 80h-A3h 36 BYTE LOOKUP TABLE (LUT) IVR CONTROL LOGIC/ REGISTERS CONTROL INITIAL VALUE REGISTER (IVR) 00h* ONLY WHEN IN LUT-ADDER MODE V+ RH ON POWER-UP POS 7Fh
DS3501
SDA
RW WIPER REGISTER (WR)
A1
LUTVAL
LUTVAL OR LUTVAL+IVR
09h* POS 00h RL
LUT and LUT Adder Mode Block Diagram (Update Mode bit = 1)
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table
Detailed Description
The DS3501 operates in one of three operating modes: Default Mode, LUT Mode, or LUT Adder Mode. In Default Mode, the DS3501 is pin and software compatible with the ISL95311. The potentiometer's wiper position is controlled by the Wiper Register (WR) and the NV Initial Value Register (IVR) via the I2C interface. In LUT Mode and LUT Adder Mode, the potentiometer's wiper position is calculated/controlled as a function of the current temperature measured by the DS3501's internal temperature sensor. The difference between the two LUT modes is the way the potentiometer wiper position is calculated. A detailed description of the three modes as well as additional features of the DS3501 follow below. Supply Voltage Monitoring The DS3501 also features an internal 8-bit supply voltage (VCC) monitor. A value of the supply voltage measurement can be read over I2C at the address 0Eh. To calculate the supply voltage, simply convert the hexadecimal result into decimal and then multiply it by the LSB as shown in the Analog Voltage Monitoring Characteristics electrical table.
DS3501
Mode Selection
The DS3501 mode of operation is determined by two bits located in Control Register 1 (CR1), which is nonvolatile. In particular, the mode is determined by the Update Mode bit (CR1.0) and the Adder Mode bit (CR1.1). Table 1 illustrates how the two control bits are used to select the operating mode. When shipped from the factory, the DS3501 is programmed with the CR1.0 bit = 0, hence configuring the DS3501 in Default Mode.
Digital Potentiometer Output
The potentiometer consists of 127 resistors in series connected between the RH and RL pins. Between each resistance and at the two end points, RH and RL, solidstate switches enable RW to be connected within the resistive network. The wiper position and the output on RW are decoded based on the value in WR. If RH, RL, and RW are externally connected in a voltage-divider configuration, then the voltage on RW can be easily calculated using the following equation: VRW = VRL + WR (VRH - VRL ) 127
Table 1. DS3501 Operating Modes
UPDATE MODE BIT (CR1.0) 0 1 1 ADDER MODE BIT (CR1.1) X 0 1 MODE Default Mode (default) LUT Mode LUT Adder Mode
Default Mode
Default Mode of the DS3501 is the simplest mode of the three. As shown in the Default Mode Block Diagram, the potentiometer is controlled by the Wiper Register/ Initial Value Register (WR/IVR). Upon power-up of the DS3501, the value stored in the NV Initial Value Register (IVR) is recalled into the volatile Wiper Register (WR). The wiper can then be changed any time after by writing the desired value to the WR/IVR Register. The WR/IVR Register is located at memory address 00h and is implemented as EEPROM shadowed SRAM. This register can be visualized as an SRAM byte (the WR portion) in parallel with a EEPROM byte (the IVR portion). The operation of the register is controlled by the Shadow EEPROM (SEE) bit, CR0.7. When the SEE bit = 0 (default), data written to memory address 00h by I2C actually gets stored in both SRAM (WR) and EEPROM (IVR). Conversely, when SEE = 1, only the SRAM (WR) is written to the new value. The EEPROM byte (IVR) continues to store the last value written to it when SEE was 0. Reading memory address 00h reads the value stored in WR. As shown in the Default Mode memory map (see Table 2), the SEE bit is volatile and its power-up default state is 0.
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where WR is the wiper position in decimal (0-127).
Temperature Conversion and Supply Voltage Monitoring
Temperature Conversion The DS3501 features an internal 8-bit temperature sensor that is capable of driving the LUT and providing a measurement of the ambient temperature over I2C by reading address 0Ch. The sensor is functional over the entire operating temperature range and is in signed two's complement format with a resolution of 1C/bit. See below for the temperature sensor's bit weights.
S 26 25 24 23 22 21 20
To calculate the temperature, treat the two's complement binary value as an unsigned binary number, then convert it to decimal. If the result is greater than or equal to 128, subtract 256 from the result.
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table DS3501
Table 2. Default Mode Memory Map
REGISTER WR/IVR CR0 CR1 CR2 NAME Wiper Register/Initial Value Control Register 0 Control Register 1 Control Register 2 ADDRESS (HEX) 00h* 02h 03h 0Ah VOLATILE/NONVOLATILE NV (Shadowed) V NV (Shadowed) V FACTORY/POWER-UP DEFAULT 40h 00h 00h 00h
*In Default Mode, both WR and IVR are accessed through memory location 00h. Refer to the Default Mode section for additional information.
Table 3. LUT Mode and LUT Adder Mode Memory Map
REGISTER IVR CR0 CR1 LUTAR WR CR2 TEMP VCC LUT0 LUT1 LUT2 -- LUT33 LUT34 LUT35 NAME Initial Value Register Control Register 0 Control Register 1 LUT Address Register Wiper Register Control Register 2 Temperature Value VCC Voltage Value Wiper Value for T -37C Wiper Value for -36C to -33C Wiper Value for -32C to -29C -- Wiper Value for +92C to +95C Wiper Value for +96C to +99C Wiper Value for T 100C ADDRESS (HEX) 00h* 02h 03h 08h 09h* 0Ah 0Ch 0Eh 80h 81h 82h -- A1h A2h A3h VOLATILE/NONVOLATILE NV (Shadowed) V NV (Shadowed) V V V V (Read-Only) V (Read-Only) NV NV NV -- NV NV NV FACTORY/POWER-UP DEFAULT 40h 00h 00h N/A N/A 00h N/A N/A 00h 00h 00h -- 00h 00h 00h
*In LUT Mode and LUT Adder Mode, the WR is accessed through memory address 09h, while IVR remains at memory address 00h.
LUT Mode
LUT Mode is selected by setting the Update Mode bit (CR1.0) to 1 and the Adder Mode bit (CR1.1) to 0. An overview of the DS3501 in this mode is illustrated in the LUT Mode and LUT Adder Mode Block Diagram. Also, the memory map for LUT Mode and LUT Adder Mode is shown in Table 3. The major difference between the two LUT modes is whether or not the value in the IVR is added to the values stored in the lookup table. The dashed line/arrow shown in the block diagram is not active in LUT mode. When in LUT Mode, on power-up the IVR value is recalled into the WR register. This value will remain there until completion of the first temperature conversion following power-up. The temperature is measured
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every tFRAME. The temperature value is used to calculate an index that points to the corresponding value in the lookup table. This index is referred to as the LUT Address Register (LUTAR). The value stored in the LUT at the location pointed to by LUTAR is called LUTVAL. The Wiper Register is then automatically loaded with LUTVAL. The process then repeats itself, continuously updating the wiper setting in a closed-loop fashion. In this mode the 36-byte LUT is populated with wiper settings for each four-degree temperature window. Valid wiper settings are 00h to 7Fh. The memory map in Table 3 shows the memory address of the LUT as well as the corresponding temperature range for each byte in the LUT. Also, the LUT features one-degree hysteresis to prevent chattering if the measured temperature
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table
falls on the boundary between two windows. As the temperature increases, the LUT changes on even temperature values (see Figure 1). Conversely, the LUT changes on odd temperature values when the temperature is decreasing.
DS3501
LUT20 MEMORY LOCATION LUT19
DECREASING TEMPERATURE
LUT Adder Mode
INCREASING TEMPERATURE
LUT18 LUT17 1C HYSTERESIS WINDOW
LUT16
24
28
32
36
40
44
TEMPERATURE (C)
LUT Adder Mode is selected by setting the Update Mode bit (CR1.0) to 1 and the Adder Mode bit (CR1.1) to 1. This mode operates similar to LUT Mode with one major difference (see the LUT Mode and LUT Adder Mode Block Diagram). The Wiper Register is loaded with the sum of LUTVAL and IVR. Furthermore, in this mode, the values programmed into the LUT are signed two's complement. This allows convenient positive or negative offsetting of the nominal IVR value.
Figure 1. LUT Hysteresis
DS3501 Control Registers
The DS3501 contains three control registers (CR0, CR1, and CR2) used to configure and control modes and features.
Control Register 0 (CR0) POWER-UP DEFAULT MEMORY TYPE 02h SEE bit7 00h Volatile Reserved Reserved Reserved Reserved Reserved Reserved Reserved bit0
bit7
SEE: Controls functionality of shadowed NV registers (such as the WR/IVR register). 0 = Data written to shadowed NV memory is stored in both SRAM and EEPROM (default). 1 = Data written to shadowed NV memory is stored only in SRAM. Reserved
bit6:0
Control Register 1 (CR1) FACTORY DEFAULT MEMORY TYPE 03h 00h Shadowed Nonvolatile Adder Mode Update Mode bit0
Reserved bit7
Reserved
Reserved
Reserved
Reserved
Reserved
bit7:2 bit1
Reserved Adder Mode: This bit is valid only if the Update Mode bit = 1. 0 = Sets the DS3501 to LUT Mode. 1 = Sets the DS3501 to LUT Adder Mode. Update Mode: 0 = Sets the DS3501 to Default Mode. In this mode the DS3501 is compatible with the ISL95311 (default). 1 = Sets the DS3501 to one of the two LUT-based modes depending on the Adder Mode bit.
bit0
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table DS3501
Control Register 2 (CR2) POWER-UP DEFAULT MEMORY TYPE 0Ah Reserved bit7 bit7:3 bit2 Reserved TEN: Temperature Update Enable bar. This bit is valid only in LUT Mode and LUT Adder Mode. 0 = Normal LUT operation. The WR is automatically loaded with LUTVAL+IVR or LUTVAL following each temperature conversion. 1 = Places the potentiometer in manual mode allowing WR (09h) to be written using I2C. AEN: Address Update Enable bar. This bit is valid only in LUT Mode and LUT Adder Mode. 0 = Normal LUT operation. LUTAR (08h) is calculated following each temperature conversion that points to the corresponding location in the LUT. 1 = Disables automatic updates of LUTAR. This allow the user to directly write to the LUTAR register in order to exercise LUT values and functionality. Standby: 0 = Normal operating mode. 1 = Standby Mode. Places the DS3501 in a low-power consumption state specified by ISTBY. The I2C interface is still active in this state. 00h Volatile Reserved Reserved Reserved Reserved TEN AEN Standby bit0
bit1
bit0
Standby Mode and ICC
The DS3501 has three specified levels of supply current. Active current during I2C communications while in the LUT-driven mode is specified as ICC, and is the "worst-case" supply current. Active current without I2C communications while in the LUT driven mode is specified as the supply current: ICC2. SDA and SCL are held statically in the high-logic level while the DS3501 continues to function in LUT-driven mode. The third level is specified as standby mode, ISTBY. This is the lowest possible current consumption mode. Standby mode is enabled with CR2.0 = 1. All internal operations are halted including internal temperature sensor results. Consequently, WR's position will not change, and will remain in the last state that was loaded into WR. I2C will, however, continue to function, and once CR2.0 = 0, the DS3501 will resume normal operation after the first temperature conversion cycle is complete (tFRAME).
MSB 0 1 0 1 0 A1 A0
LSB R/W
SLAVE ADDRESS* *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1.
Figure 2. DS3501 Slave Address Byte
result in a 0 in the corresponding bit position in the slave address. Conversely, address pins tied to VCC result in a 1 in the corresponding bit positions. For example, the DS3501's slave address byte is 50h when A0 and A1 pins are grounded. I2C communication is described in detail in the I 2 C Serial Interface Description section.
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe I2C data transfers. (See Figure 3 and I2C AC Electrical Table for additional information.) Master device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions.
Slave Address Byte and Address Pins
The slave address byte consists of a 7-bit slave address plus a R/W bit (see Figure 2). The DS3501's slave address is determined by the state of the A0 and A1 address pins. These pins allow up to four devices to reside on the same I2C bus. Address pins tied to GND
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table DS3501
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN).
Figure 3. I2C Timing Diagram
Slave devices: Slave devices send and receive data at the master's request. Bus idle or not busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. START condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. STOP condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. Repeated START condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. Bit write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL. Bit read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledge (ACK and NACK): An Acknowledge (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a 0 during the 9th bit. A device performs a NACK by transmitting a 1 during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or indicates that the device is not receiving data. Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgment is read using the bit read definition. Byte read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to ter11
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table
minate communication so the slave will return control of SDA to the master. Slave address byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The slave address byte of the DS3501 is shown in Figure 2. When the R/W bit is 0 (such as in 50h), the master is indicating it will write data to the slave. If R/W = 1 (51h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS3501 assumes the master is communicating with another I2C device and ignores the communication until the next START condition is sent. Memory address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. of 8 (08h, 10h, 18h, etc). Attempts to write to additional pages of memory without sending a STOP condition between pages results in the address counter wrapping around to the beginning of the present row. To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus-free or EEPROM-write time to elapse. Then the master can generate a new START condition and write the slave address byte (R/W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge polling: Any time a EEPROM byte is written, the DS3501 requires the EEPROM write time (tW) after the STOP condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device will not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS3501, which allows communication to continue as soon as the DS3501 is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device. EEPROM write cycles: The DS3501's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature (hot) as well as at room temperature. Writing to shadowed EEPROM with SEE = 1 does not count as a EEPROM write. Reading a single byte from a slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. Manipulating the address counter for reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. See Figure 4 for a read example using the repeated START condition to specify the starting memory location.
DS3501
I2C Communication Writing a single byte to a slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave's acknowledgment during all byte write operations. When writing to the DS3501, the potentiometer will adjust to the new setting once it has acknowledged the new data that is being written, and the EEPROM (if SEE = 0) will be written following the STOP condition at the end of the write command. To change the setting without changing the EEPROM, terminate the write with a repeated START condition before the next STOP condition occurs. Using a repeated START condition prevents the tW delay required for the EEPROM write cycle to finish.
Writing multiple bytes to a slave: To write multiple bytes to a slave in one transaction, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. The DS3501 is capable of writing 1 to 8 bytes (1 page or row) in a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). The first page begins at address 00h and subsequent pages begin at multiples
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table DS3501
TYPICAL I2C WRITE TRANSACTION MSB START 0 1 0 1 0 A1 A0 LSB R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER ADDRESS *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
DATA
EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE CONNECTED TO GND). 50h A) SINGLE-BYTE WRITE -WRITE LUTAR REGISTER TO 00h B) SINGLE-BYTE READ -READ CR0 REGISTER 08h SLAVE 0 0 0 0 0 0 0 0 ACK SLAVE ACK 51h REPEATED START 01h SLAVE ACK 0000 0 0 0 1 SLAVE ACK STOP 0 1 0 1 0 0 0 1 SLAVE ACK DATA MASTER NACK STOP STOP
START 0 1 0 1 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 ACK 50h 02h
START 0 1 0 1 0 0 0 0 SLAVE 0 0 0 0 0 0 1 0 SLAVE ACK ACK 50h CR1 (03h) SLAVE ACK 00000 011
C) SINGLE-BYTE WRITE SET TO LUT MODE
START 0 1 0 1 0 0 0 0
50h D) TWO-BYTE WRITE - WRITE 80h AND 81h TO 00h START 0 1 0 1 0 0 0 0 SLAVE ACK
80h 10000 000 SLAVE ACK
00h 0000 0 0 0 0 SLAVE ACK
00h 0000 0 0 0 0 SLAVE ACK STOP
50h E) TWO-BYTE READ - READ 80h AND 81H START 0 1 0 1 0 0 0 0 SLAVE ACK
80h 10000 000 SLAVE ACK REPEATED START
51h 0101 0 0 0 1 SLAVE ACK
DATA LUT 0 MASTER ACK
DATA LUT 1 MASTER ACK STOP
Figure 4. I2C Communication Examples
Reading multiple bytes from a slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it must NACK to indicate the end of the transfer and generates a STOP condition.
SDA and SCL Pullup Resistors
SDA is an I/O with an open-collector output that requires a pullup resistor to realize high-logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the AC electrical characteristics are within specification. A typical value for the pullup resistors is 4.7k.
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3501, decouple both the power-supply pin and the wiper-bias voltage pin with a 0.01F or 0.1F capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications.
Chip Information
TRANSISTOR COUNT: 22,400 SUBSTRATE CONNECTED TO GROUND
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High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table DS3501
Typical Operating Circuit
R1 GATE 1 TFT G1 B1
CSTOR
CLCD
GATE 2
GATE 3
VCOM 2.7V 15.0V
I2C
SDA SCL A0 A1
VCC
V+
RH RW
DS3501
GND RL
Pin Configuration
TOP VIEW
SDA 1 GND VCC 2 3 10 SCL 9 V+ RL RW RH
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
DS3501
8 7 6
A1 4 A0 5
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Heaney

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